Power management systems and methods

ABSTRACT

Systems and methods for efficiently managing power consumption in portable electronic devices are provided. In one embodiment, power management circuitry may operate the device in a low power mode (e.g., a HIBERNATION mode), but enables the device to quickly become fully operational in response to a power-ON event, despite having been in that low power mode. This may be accomplished by powering a processor engaging memory (e.g., SDRAM) while other circuitry are powered OFF. In another embodiment, the display may be driven by an application portion when operating in an ON mode, but may be driven by a carrier portion when the application is operating in a low power mode. In another embodiment, various discrete circuitry portions are selectively turned ON and OFF, depending, for example, on whether a particular discrete circuitry portion is idle or its processing functionality is not needed.

This application is a division of patent application Ser. No.11/650,073, filed Jan. 4, 2007, which is hereby incorporated byreference herein in its entirety.

BACKGROUND OF THE INVENTION

This relates to electronic devices and more particularly to powermanagement methods and systems.

Portable electronic devices, such as wireless and cellular telephones,digital media players (e.g., music players and video players), andhybrid devices that combine telephone and media playing functionalityare known. These devices are typically powered by one or more batteries.

Batteries store a fixed amount of energy. Therefore, efficient use ofthe fixed energy source may be required to ensure the media device canoperate for at least a predetermined amount of time, before beingreplaced or recharged. Thus, a need for efficient power management hasbecome increasingly important, especially given the trend inminiaturization (and corresponding decrease in battery energy storagecapacity), coupled with a demand for providing more power consumingfeatures (e.g., devices providing both media playing and telephonefunctionality, as well as relatively large color display screens).

Accordingly, what is needed are power management methods and systems forefficiently managing power consumption in portable electronic devices,including media devices.

SUMMARY OF THE INVENTION

Systems and methods for efficiently managing power consumption inportable electronic, such as those that include media playing andtelephone functionality, are provided.

In one embodiment, power management may be implemented in a deviceincluding an application portion and a carrier portion. The carrierportion can include circuitry for performing telephone functions (e.g.,transmitting data to and receiving data from a communications tower).The carrier circuitry can include circuitry for other wirelesscommunication functions, such as to enable Bluetooth and Wi-Ficommunication methods. The application portion may include all othercircuitry not specifically reserved for the carrier circuitry. Forexample, the application portion may include a processor, memory (e.g.,for storing media files), SDRAM, a display, and other circuitry.

The application and carrier portions may each operate according topredetermined power modes. For example, the application portion mayoperate according to an OFF mode, a DEEP SLEEP mode, a SLEEP mode, aHIBERNATE mode, and an ON mode. The carrier portion may operateaccording to an OFF mode, a SLEEP mode, and an ON mode. Depending onwhich mode the application portion, the carrier portion, or thecombination of both portions is operating in, power management circuitrycan use an appropriate power management scheme to conserve power.

In one embodiment of a power management scheme according to theinvention, the power management circuitry may operate in a low powermode (e.g., a HIBERNATION mode), but enable the device to quickly becomefully operational in response to a power-ON event (e.g., an event thatcauses the media device to switch from a low power mode to an ON mode).To provide the combined benefit of both low power consumption and quickoperational readiness, a processor engaging memory (e.g., SDRAM) may bepowered ON while other circuitry in the application portion and thecarrier portion are powered OFF. By keeping the processor engagingmemory powered ON, a time delay in powering up that memory can beavoided when the device switches from a low power mode to an ON mode.This can enable the memory to substantially immediately load itscontents into the processor. When the processor receives the memorycontents, the media device may be fully operational.

When the media device is in the low power mode, both the application andcarrier portions may be in a low power mode. The power managementcircuitry may periodically activate the carrier portion (orpredetermined circuitry within the carrier portion) to enable it to, forexample, determine whether an incoming signal (e.g., telephone call ortext message) is being received. If an incoming signal is beingreceived, this may trigger a power-ON event that causes the powermanagement circuitry to switch the media device from a low power mode toan ON mode. If no incoming signal is detected, the power managementcircuitry may deactivate the carrier portion, allowing it to return to alow power mode.

Power management may coordinate power management across both portions ofthe personal media device. This provides extra flexibility in managingpower consumption. For example, independent mode control may beexercised for the application portion and the carrier portion. That is,when the application portion is operating in a particular mode (e.g., ONmode), the power management circuitry may select one of severalavailable modes (e.g., OFF, SLEEP, and ON) for the carrier circuitry.The available modes may depend on the operating mode of the applicationportion.

Power management may also be used to control how content is displayed ona display screen of the personal media device. For example, when theapplication portion is operating in an ON mode, the processor may drivethe display. However, when the application portion is operating in a lowpower mode, the carrier portion may drive the display. The carrierportion may write data to memory local to the display during the SLEEPmode interval (e.g., once every second). The data stored in the localmemory may then be displayed on the display. Power savings may berealized using the carrier portion to drive the display when the deviceis operating in a low power mode because the carrier portion does notrequire processor activation, which may require more power than thecarrier portion to drive the display.

Power management may also be used to reduce power consumption when thedevice is operating in an ON mode. For example, various discretecircuitry portions can be selectively turned ON and OFF, depending, forexample, on whether a particular discrete circuitry portion is idle orits processing functionality is not needed. The discrete circuitryportions may be turned ON and OFF by electrically coupling andde-coupling the circuitry portion to a power supply via a controlledswitch. When a discrete circuitry portion is not needed, the supply ofpower is cut off, thereby preventing power loss caused by leakagecurrent.

In one embodiment, the switch may be controlled by interrupt controlcircuitry and/or by the processor. The interrupt control circuitry maybe operative to cause a switch to close, thereby electrically couplingthe discrete circuitry portion associated with that switch to the powersupply. When the processor is turned OFF and the processor is needed toperform a function, the interrupt circuitry may cause the processorswitch to close to enable power to be delivered to the processor. Whenthe processor is ON, it may monitor itself and other discrete circuitryportions to determine whether to turn itself or those portions OFF. Ifthe discrete circuitry portion is not needed (e.g., idling), the processmay provide an instruction that causes a switch associated with thatportion to electrically de-couple the supplied power from that portion.In addition, the processor may provide instructions to cause a switch toelectrically couple a discrete circuitry portion to the power supply.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present invention, its nature andvarious advantages will become more apparent upon consideration of thefollowing detailed description, taken in conjunction with theaccompanying drawings, in which like reference characters refer to likeparts throughout, and in which:

FIG. 1 shows a simplified block diagram of portable electronic device inaccordance with an embodiment of the present invention;

FIG. 2 is a more detailed but simplified block diagram of a device inaccordance with an embodiment of the present invention;

FIG. 3 shows how the application portion of a device may change statesin accordance with an embodiment of the present invention;

FIG. 4 shows how the carrier portion of a device may change states inaccordance with an embodiment of the present invention;

FIG. 5 shows a power management coordination table in accordance with anembodiment of the present invention;

FIG. 6 is a flowchart illustrating steps of a power management schemeaccording to an embodiment of the present invention the invention;

FIG. 7 is a flowchart illustrating steps of another power managementscheme according to an embodiment of the present invention theinvention;

FIG. 8 is a flowchart of a power management scheme involving a displayin accordance with an embodiment of the present invention;

FIG. 9 is a flowchart of another of power management scheme involving adisplay in accordance with an embodiment of the present invention;

FIG. 10 shows a simplified block diagram for implementing a powermanagement to reduce power consumption when a device is operating in anON mode in accordance with an embodiment of the present invention;

FIG. 11 is a flowchart for implementing power management to reduce powerconsumption when the a device is operating in an ON mode in accordancewith an embodiment of the present invention;

FIG. 12 is another flowchart for implementing power management to reducepower consumption when the media device is operating in an ON mode inaccordance with an embodiment of the present invention;

FIG. 13 is an illustrative timing diagram showing the ON/OFF states andActive/Idle states of a processor and first and second discretecircuitry in accordance with an embodiment of the present invention;

FIG. 14 is yet another flowchart for implementing power management toreduce power consumption when a device is operating in an ON mode inaccordance with an embodiment of the present invention; and

FIG. 15 is an illustrative timing diagram showing the ON/OFF states of aprocessor and first, second and third discrete circuitry in accordancewith an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a simplified block diagram of illustrative portable mediaplayer 100. Media player 100 may include processor 102, storage device104, user interface 108, display 110, CODEC 112, power managementcircuitry 116, bus 118, memory 120, communications circuitry 122, andpower management circuitry for communications circuitry 123. Processor102 can control the operation of many functions and other circuitryincluded in media player 100. Processor 102 may drive display 110 andmay receive user inputs from user interface 108.

Storage device 104 may store media (e.g., music and video files),software (e.g., for implementing functions on device 100, preferenceinformation (e.g., media playback preferences), lifestyle information(e.g., food preferences), exercise information (e.g., informationobtained by exercise monitoring equipment), transaction information(e.g., information such as credit card information), wireless connectioninformation (e.g., information that may enable device to establish awireless connection such as a telephone connection), subscriptioninformation (e.g., information that keeps tracks of podcasts ortelevision shows or other media a user subscribes to), telephoneinformation (e.g., telephone numbers), and any other suitable data.Storage device 104 may include one more storage mediums, including forexample, a hard-drive, permanent memory such as ROM, semi-permanentmemory such as RAM, or cache.

Memory 120 may include one or more different types of memory which maybe used for performing device functions. For example, memory 120 mayinclude cache, Flash, ROM, and/or RAM. Memory may be specificallydedicated to storing firmware. For example, memory may be provided forstore firmware for device applications (e.g., operating system, userinterface functions, and processor functions).

Power management circuitry 116 may be provided for controlling powermanagement schemes in accordance with the principles of the presentinvention. Power management circuitry 116 may communicate with othercircuitry in device 100 directly (not shown in this FIG., but shown inFIG. 2) or indirectly via bus 118.

Bus 118 may provide a data transfer path for transferring data to, from,or between storage device 104, power management circuitry 116,communications circuitry 123, baseband circuitry 124, memory 120, andprocessor 102. Coder/decoder (CODEC) 112 may be included to convertdigital audio signals into an analog signal, which may be provided to anoutput port (not shown).

Communications circuitry 122 may be included in a carrier circuitryportion (delimited by dashed lines 125) of device 100. Carrier circuitryportion 125 may be dedicated primarily to processing telephone functionsand other wireless communications (e.g., Wi-Fi or Bluetooth). Inaddition, power management of carrier circuitry portion 125 may becontrolled by power management circuitry 116 and/or power managementcircuitry 123, which may be dedicated specifically to communicationscircuitry 122. It is understood that the carrier circuitry portionoperate independent of other device components operating in device 100.That is, carrier circuitry may be an independently operating subsystemwithin device 100 that may communicate with other components withindevice 100.

User interface 108 may allow a user to interact with the player 100. Forexample, the user input device 108 can take a variety of forms, such asa button, keypad, dial, a click wheel, or a touch screen. Communicationscircuitry 122 may include circuitry for wireless communication (e.g.,short-range and/or long range communication). For example, the wirelesscommunication circuitry may be Wi-Fi enabling circuitry that permitswireless communication according to one of the 802.11 standards or aprivate network. Other wireless network protocols standards could alsobe used, either in alternative to the identified protocols or inaddition to the identified protocol. Another network standard may beBluetooth.

Communications circuitry 122 may also include circuitry that enablesdevice 100 to be electrically coupled to another device (e.g., acomputer or an accessory device) and communicate with that other device.As indicated above, communications circuitry 122 may also includebaseband circuitry for performing relatively long-range communications(e.g., telephone communications). If desired, communications circuitry122 may include circuitry for supporting both relatively long-range andshort-range communications. For example, communications circuitry 122may support telephone, Wi-Fi, and Bluetooth communications.

In one embodiment, player 100 may be a portable computing devicededicated to processing media, such as audio and video. For example,device 100 may be a media player (e.g., MP3 player), a game player, aremote controller, a portable communication device, a remote orderinginterface, an audio tour player, or other suitable personal device.

In another embodiment, player 100 may be a portable device dedicated toproviding media processing and telephone functionality in singleintegrated unit. Device 100 may be battery-operated and highly portableso as to allow a user to listen to music, play games or video, recordvideo or take pictures, place and take telephone calls, communicate withothers, control other devices, and any combination thereof. In addition,device 100 may be sized such that is fits relatively easily into apocket or hand of the user. By being handheld, device 100 is relativelysmall and easily handled and utilized by its user and thus may be takenpractically anywhere the user travels.

FIG. 2 is a more detailed but simplified block diagram of illustrativedevice 200. Device 200 may be a mobile telephone. FIG. 2 showsillustrative application circuitry portion 210 and carrier circuitryportion 260. Carrier portion 260 can include circuitry for performingtelephone functions (e.g., transmitting data to and receiving data froma communications tower), such as baseband circuitry 262. Carriercircuitry 260 may also include circuitry (not shown) for other wirelesscommunication functions such as Bluetooth and Wi-Fi.

Application portion 210 may include all other circuitry not specificallyreserved for carrier portion 260. For example, application portion 210may include processor 212, storage circuitry 214 (e.g., for storingmedia files), SDRAM 216, a display 220, and other circuitry, which iscollectively represented by box 230. Application portion 210 may alsoinclude power management circuitry 240 in accordance with the principlesof the present invention. Power management circuitry 240 may genericallyrepresent circuitry for controlling power management of applicationportion 210 and carrier portion 260. Power management circuitry 240 mayoperate in conjunction with carrier power management circuitry (notshown) of carrier portion 260 when implementing power managing schemesin accordance with the invention.

Storage circuitry 214 may be similar to storage circuitry 104 discussedabove in connection with FIG. 1. SDRAM 216 may provide content (e.g.,instructions) to processor 212 that may enable processor 212 to executefunctions of device 200. In certain circumstances, SDRAM 216 may“engage” or “prep” processor 212 by providing it with data to performone or more functions when device 200 switches from a low power mode toan ON mode (discussed in more detail below). SDRAM 216 may be referredto herein as processor engagement circuitry. For example, when device200 is operating in a low power mode, SDRAM 216 may store data that maybe used to “engage” processor 212 so it knows, for example, a status ofdevice 200 and operate accordingly. In some embodiments, processor 212and SDRAM 216 may be integrated into a single package. For example,package-on-package technology may be used to provide an integratedprocessor and memory package.

Display 220 may be any suitable display for displaying media, includinggraphics, text, and video. In some embodiments, display may be a touchscreen display or an LCD. Display 220 may be driven by processor 212 orbaseband circuitry 262. When driven by processor 212, a higher bit rateof data may be provided, thereby enabling the display of high resolutiongraphics, video, and other content to be displayed on display 220. Whendriven by baseband circuitry 262, a lower bit rate of data may beprovided to display screen 220. The data provided by baseband circuitry262 may be written to memory 222, which may be memory local to display220, the contents of which are displayed on display 220. For example,content written to memory 222 and displayed on display 220 may include aclock, a signal strength indicator, and a battery power indicator. Thiscontent may be provided by processor 212 or baseband circuitry 262.Though the quantity of data may be less than that provided by processor212, power consumption may be lower when driving display 220 withbaseband circuitry 262 than when being driven by processor 212.

The application portion (e.g., application portion 210) and the carrierportion (carrier portion 260) may each operate according topredetermined power modes. FIG. 3 shows that the application portion mayoperate according to an OFF mode, a DEEP SLEEP mode, a SLEEP mode, aHIBERNATE mode, and an ON mode in accordance with the principles of thepresent invention. The OFF mode may represent a state where a powersource (e.g., battery) has been removed from the device. In the DEEPSLEEP mode, the power source (e.g., battery) is connected to the device,but is not powering any circuitry, except power management circuitry(e.g., circuitry 240 of FIG. 2). In the SLEEP mode, all circuitry may bepowered, but the clock or clocks needed for enabling the device toexecute functions are not running. In the HIBERNATE mode, the powermanagement circuitry and the engagement processor memory (e.g., SDRAM216 of FIG. 2) may be powered (as well as other circuitry requiringpower to power the processor memory) and a clock may be provided torefresh the engagement processor memory. The other circuitry (e.g.,circuitry that may be powered in the SLEEP mode) may not receive powerin the HIBERNATE mode. Thus, the engagement processor memory can bemaintained in a ready-to-enable processor state when the device is in alow power mode. The other low power modes may include DEEP SLEEP andSLEEP. The ON mode may represent a mode where circuitry is powered (whensuch power is required) and clocks are available for enabling the deviceto execute one or more functions.

FIG. 3 also shows how the application portion of the device may changebetween states. As shown, the ON, HIBERNATE, SLEEP, and DEEP SLEEP modesmay all switch to the OFF mode. The application portion may switchbetween the ON and DEEP SLEEP modes, between the ON and SLEEP modes, andthe ON and HIBERNATE modes. The application portion may be able toswitch between different modes not specifically shown in FIG. 3. Forexample, the application portion may be able to switch between theHIBERNATE and SLEEP modes.

The carrier portion (e.g., carrier portion 260) may operate according toan OFF mode, a SLEEP mode, and an ON mode. The OFF mode may occur when apower source (e.g., a battery) is not connected to the device. In theSLEEP mode (also the low power mode of the carrier circuitry), thecarrier circuitry may be powered, but is in a minimally active state.That is power may be provided, but no functions are being performed. Inthe ON mode, one or more carrier portion functions may be executed. FIG.4 also shows how the carrier portion of the device may change betweenstates. As shown, the ON and SLEEP modes may all switch to the OFF mode.The carrier portion may switch between the ON and SLEEP modes

Power management according to the invention may coordinate powermanagement across both portions of the device. This provides extraflexibility in managing power consumption. For example, independent modecontrol may be exercised for the application portion and the carrierportion. That is, when the application portion is operating in aparticular mode (e.g., ON mode), the power management circuitry mayselect one of several available modes (e.g., OFF, SLEEP, and ON) for thecarrier circuitry. The available modes may depend on the operating modeof the application portion. A power management mode coordination tablefor the application and carrier portions is illustrated in FIG. 5.

FIG. 5 shows the three power management modes of the carrier portionalong the y-axis of the table and the five power modes of theapplication portion along the x-axis of the table. The checkmarksindicate that both application and carrier portions may exist in thepower modes defined by the x and y coordinates of a box. The “X's”indicate where the power modes defined by the box at a particular x andy coordinate may not exist both application and carrier portions. Forexample, both the application and carrier portions may simultaneouslyexist in OFF modes. However, the carrier portion may not operate in anON mode when the application portion is operating in an OFF mode.

In one embodiment, the power management circuitry may operate the devicein a low power mode (e.g., a HIBERNATION mode), but enable the device toquickly become fully operational in response to a power-ON event (e.g.,an event that causes the device to switch from a low power mode to an ONmode), despite having been in that low power mode. To provide thecombined benefit of both low power consumption and quick operationalreadiness, a processor engaging memory (e.g., SDRAM) may be powered ONwhile other circuitry in the application portion and the carrier portionare powered OFF. By keeping the processor engaging memory powered ON, atime delay in powering up that memory is avoided when the deviceswitches from a low power mode to an ON mode, thereby enabling thememory to substantially immediately load its contents into theprocessor. When the processor receives the memory contents, the devicemay be fully operational.

FIG. 6 is an illustrative flowchart showing various steps of a powermanagement scheme according to the invention. At step 610, a device mayoperate in a low power mode. For example, the application portion of thedevice may be operating in the HIBERNATION mode.

At step 620, power may be provided to a processor engaging memory whilethe device is operating in the low power mode. For example, in aHIBERNATION mode, the processor engaging memory may be provided withpower and refreshed with clocks while other circuitry, such as theprocessor, may not be supplied with power.

At step 630, the device can be monitored for a power-ON event. Apower-ON event may be any event that causes the device to switch fromone power mode to another. For example, a power-ON event may occur whenthe user uses an interface of the device (e.g., to change the volume) orwhen a telephone call or text message is received. Briefly referring toFIG. 2, a power-ON event may be received at input 242 at powermanagement circuitry 240. In response to receiving the power-ON event,the power management circuitry may switch the device from the low powermode to the ON power mode, as indicated by step 640.

When the device is operating in an ON power mode, power may be providedto circuitry other than the processor engaging memory, such othercircuitry may include a processor, as indicated at step 650. At step660, the contents of the processor engaging memory may be loaded intothe processor. Assuming that the device is switching from a HIBERNATIONmode to an ON mode, the processor engaging memory is “active” and readyto substantially immediately supply the processor with its contents toenable the processor to execute one or more desired functions, asindicated at step 670.

It is understood that the steps shown in FIG. 6 are merely illustrativeand that existing steps may be modified, added or omitted.

FIG. 7 is an illustrative flowchart showing various steps of anotherpower management scheme according to the invention. This flowchartrefers to a power management scheme of the carrier portion. Starting atstep 710, the carrier portion of a personal device can be operating in aSLEEP mode. At step 720, the carrier portion (or at least a portion ofthe carrier portion) is temporarily activated once every predeterminedperiod of time to determine whether an incoming signal is beingreceived. The incoming signal may be, for example, a telephone call or atext message. Note that based on the coordination table of FIG. 5, thecarrier portion may not be temporarily operated in the ON mode as thatmay require the application portion to switch to an ON mode. Thus, whenthe carrier portion is temporarily activated, the activated portion mayoperate while the carrier portion is operating in the SLEEP mode.

A determination may be made as to whether an incoming signal is beingreceived at step 730. This determination may be made while the carrierportion is temporarily activated. If no incoming signal is beingreceived, the process may revert to step 710, where the carrier portionreturns to operate in a SLEEP power mode. If an incoming signal is beingreceived, the process may proceed to step 740, where the carrier portionis switched from the SLEEP mode to the ON mode.

It is understood that the steps shown in

FIG. 7 are merely illustrative and that existing steps may be modified,added or omitted. For example, a step may be added to show that theapplication portion may be switched to an ON mode if it is not alreadyin that mode. The application portion may have to be in the ON mode whenthe carrier portion is in the ON mode, as required by the coordinationtable of FIG. 5.

Power management according to the invention may be used to control howcontent is displayed on a display screen of the device. For example,when the application portion is operating in an ON mode, the processormay drive the display. However, when the application portion isoperating in a low power mode, the carrier portion may drive thedisplay. The carrier portion, while in the SLEEP mode, may write data tomemory local to the display (e.g., memory 222 of FIG. 2). The datastored in the local memory may then be displayed on the display. Powersavings may be realized using the carrier portion to drive the displaywhen the device is operating in a low power mode because the carrierportion does not require processor activation, which may require morepower than the carrier portion to drive the display.

FIG. 8 is a flowchart of a power management scheme involving a displayin accordance with the principles of the present invention. Starting atstep 810, the application portion of the device may drive a display whenthe application portion is operating in an ON mode. For example, theprocessor (e.g., processor 212 of FIG. 2) may drive the display when theapplication portion is operating in the ON mode. Referring to FIG. 2,processor 212 may drive display 220 by providing data over path 232and/or the combination of path 234 and multiplexor 236. Data provided tomultiplex 236, regardless of whether it is provided by processor 212 orcarrier portion 260, may be written to memory 222.

The carrier portion of the device may be used to drive the display whenthe application portion is operating in a low power mode, as indicatedin step 820. For example, when the application portion switches from theON mode to one of the HIBERNATE or SLEEP modes (based on thecoordination table of FIG. 5), the carrier circuitry may drive thedisplay. Referring to FIG. 2, baseband circuitry 262 may provide dataover path 237 to multiplexor 236, which provides the data to memory 222of display 220. It is understood that although it may be preferable forthe application processor to drive the memory driven portion of thedisplay when operating in the ON mode, the carrier portion may drive thememory driven portion of the display when the application portion isoperating in the ON mode.

It is understood that the steps shown in FIG. 8 are merely illustrativeand that existing steps may be modified, added or omitted.

FIG. 9 is a flowchart showing another of power management schemeinvolving a display in accordance with the principles of the presentinvention. Starting at step 910, the magnitude of a signal can bemonitored. The signal may be power signal provided to the processor ofthe application portion of the device. When the application portion isoperating in the ON mode, the voltage provided to the processor may beat, or above, a predetermined voltage level. At step 920, adetermination is made if the magnitude of the signal is at, or above, apredetermined magnitude. If yes, then the processor may be used to drivethe display, as indicated at step 922. If no, then the process proceedsto step 930, where the baseband circuitry may be used to drive thedisplay. For example, as long as the magnitude of the signal is at orabove the predetermined magnitude, a multiplexor (e.g., multiplexor 236)may receive a selection input (e.g., input 238 to transmit data receivedfrom the processor. When the magnitude of the signal drops below thepredetermined magnitude, the multiplexor input signal may be set totransmit data received by the baseband circuitry.

The data received by the baseband circuitry may be written to the memorylocal to the display, as specified in step 932. At step 934, informationbased on the contents stored in the memory local to the display may bedisplayed.

It is understood that the steps shown in FIG. 9 are merely illustrativeand that existing steps may be modified, added or omitted.

FIG. 10 shows an illustrative simplified block diagram for implementinga power management to reduce power consumption when the device isoperating in an ON mode in accordance with the principles of the presentinvention. FIG. 10 may include discrete circuitry portions 1010, 1020,1030, and 1040, each of which have an associated switch 1012, 1022,1032, and 1042 operative to electrically couple or decouple itsassociated circuitry portion to a power source. Discrete circuitryportions 1010, 1020, 1030, and 1040 may be discrete in that they may beselectively powered ON and OFF independent of each other. In addition,they may be discrete in that they may each perform specific functions.For example, portion 1010 may be a processor such as an ARM processor,portion 1020 may perform render 3D graphics, portion 1030 may handleMPEG-4 protocols, and portion 1040 may perform a function associatedwith other circuitry. Note that additional discrete portions may beprovided, but have been omitted to avoid overcrowding the drawing.Discrete portions may be included only in the application portion, maybe included only in the carrier portion, or may be included in both theapplication and carrier portions.

The discrete circuitry portions are selectively turned ON and OFF,depending, for example, on whether a particular discrete circuitryportion is idle or its processing functionality is not needed. Thediscrete circuitry portions may be turned ON and OFF by electricallycoupling and de-coupling the circuitry portion to a power supply via acontrolled switch (e.g., switches 1012, 1022, 1032, and 1042). When adiscrete circuitry portion is not needed, the supply of power is cutoff, thereby preventing power loss caused by leakage current.

The switch may be controlled by interrupt control circuitry 1030 and/orby the processor portion 1010. Interrupt control circuitry 1050 may beoperative to cause switch 1012 to close, thereby electrically couplingprocessor 1010 to the power supply. When processor 1010 is turned OFFand processor 1010 is needed to perform a function, interrupt circuitry1050 may cause switch 1012 to close to enable power to be delivered toprocessor 1010. Interrupt circuitry 1050 may be responsive to signalsreceived at input 1052.

Interrupt circuitry is shown coupled to switch 1012, but it mayoptionally be coupled to switches 1022, 1032, and 1042. In the lattercoupling arrangement, an interrupt signal provided by circuitry 1050 maycause each portion to be electrically coupled to the power supply.

When the processor is ON, it may monitor itself and other discretecircuitry portions 1020, 1030, and 1040 to determine whether to turnthose portions OFF. If the discrete circuitry portion is not needed(e.g., idling), processor 1010 may provide an instruction that causes aswitch associated with that portion to electrically de-couple thesupplied power from that portion. For example, if processor 1010determines that portion 1020 is not needed, it may provide aninstruction that causes switch 1022 to open. In addition, processor 1010may provide instructions to cause a switch to electrically couple adiscrete circuitry portion to the power supply. For example, processormay provide an instruction to switch 1032 to close so that portion 1030is electrically coupled to the power supply.

FIG. 11 is a flowchart for implementing power management to reduce powerconsumption when the device is operating in an ON mode in accordancewith the principles of the present invention. Starting at step 1110, adetermination is made whether a discrete circuitry portion is idling orno longer needed. The processor may know that a particular discreteportion is no longer needed after a certain instruction set is carriedout by that discrete portion. Therefore, it may provide an instruction,for example, at the end of the instruction set being sent to thatportion to selectively power off that discrete portion OFF. A discreteportion may be deemed idle if it does not perform a function for atleast a predetermined period of time. If at step 1110, the determinationis no, the process may return to the beginning of step 1110. If at step1110, the determination is yes, the process may proceed to step 1120,where that discrete portion is selectively powered OFF.

At step 1130, a determination is made whether the discrete portion isneeded, for example, to perform a function. If no, then the processreturns to the beginning of step 1130. If yes, then the process proceedsto step 1140, where that discrete circuitry portion is selectivelypowered ON.

FIG. 12 is another flowchart for implementing power management to reducepower consumption when the device is operating in an ON mode inaccordance with the principles of the present invention. Starting atstep 1210, an interrupt is provided. At step 1220, a processor may bepowered ON. For example, the interrupt control circuitry may provide asignal to a switch (e.g., switch 1012) that electrically couples theprocessor to a power source. At step 1230, the processor may be used toselectively power ON and OFF one or more discrete circuitry portions.These discrete portions may be portions other than the processor. Atstep 1240, data may be provided to one or more of the discrete portionswhen powered ON. In this step, the discrete portions may include theprocessor. At step 1250, the processor may provide an instruction topower OFF the processor.

FIG. 13 is an exemplary timing diagram showing the ON/OFF states andActive/Idle states of a processor and first and second discretecircuitry. At time t₀, the processor and first discrete circuitry can bepowered ON and active, whereas the second discrete circuitry can bepowered OFF and idle. At time t₁, the second discrete circuitry can bepowered ON and active in response to receiving power ON instruction fromthe processor. Then, at time after t₂, but before time t₃, the processormay detect that the second circuitry is idle and provide a power OFFinstruction to turn second circuitry OFF. That turn-OFF instruction maybe provided prior to time t₃, at which point the process goes idle. Theturn-OFF instruction may be processed at time t₄, at which point thesecond circuitry is no longer provided with power. Even though theprocess turn OFF instruction is received after the process is no longeractive, the turn-OFF instruction may be registered, thereby enablingprocessor instructions to be carried out after the processor has enteredan idle state or powered OFF.

At time t₅, the processor may be powered OFF in response to a monitoredidle event. An example where registered processor instructions can turnOFF circuitry after the processor has been powered OFF is shown at timet₇, where first circuitry is powered OFF. Time t₆ is when firstcircuitry switches from active to idle. At time t₈, an interrupt signalis provided, which causes processor to be turned ON and rendered active.The processor may then provide commands to power up other discretecircuitry such as second circuitry at time t₉.

FIG. 14 is another flowchart for illustrative implementing powermanagement to reduce power consumption when the device is operating inan ON mode in accordance with the principles of the present invention.Starting at step 1410, an interrupt signal can be provided. Thisinterrupt signal may result in powering ON all discrete circuitryportions, as indicated at step 1420. This is illustrated in the timingdiagram of FIG. 15. As shown, at time t₀, the processor and firstthrough third discrete circuitry can be powered OFF. At time t₁, aninterrupt signal can be provided, which results in the processor and thefirst through third circuitry to be powered ON at time t₂.

Referring back to FIG. 14, at step 1430 one of the discrete circuitryportions (e.g., the processor) may be used to provide instructions topower

OFF one or more discrete circuitry portions. For example, in FIG. 15,second circuitry can be powered OFF at time t₃, and third circuitry canbe powered OFF at time t₄. At time t₅, third circuitry may powered backON. At time t₅, the first circuitry may be powered OFF. Then at time t₆,the processor may be powered OFF.

Thus it is seen that systems and methods managing power are provided. Itis understood that the steps shown in the flowcharts discussed above aremerely illustrative and that existing steps may be modified, added oromitted. Those skilled in the art will appreciate that the invention canbe practiced by other than the described embodiments, which arepresented for purposes of illustration rather than of limitation, andthe invention is limited only by the claims which follow.

1. A method for managing power consumption in a portable electronicdevice, the method comprising: operating the device in a low power mode,the low power operating mode further comprising providing power to aprocessor engaging memory; monitoring the device for a power-ON event;and switching from the low power mode to an ON power mode in the eventof a monitored power-ON event.
 2. The method of claim 1, furthercomprising: powering OFF a processor while the device is in the lowpower mode.
 3. The method of claim 1, wherein the low power mode is aHIBERNATION power mode.
 4. The method of claim 1, wherein the processorengaging memory is SDRAM.
 5. The method of claim 1, wherein in the ONpower mode, further comprising: providing power to a processor; andloading the processor with contents contained in the processor engagingmemory.
 6. The method of claim 1, wherein the low power operating modefurther comprising: providing power only to circuitry necessary forpowering the processor engagement circuitry.
 7. A portable electronicdevice comprising an application portion and a carrier portion, thetelephone comprising: power management circuitry electrically coupled tothe application and carrier portions, the power management circuitryoperative to: power OFF at least a processor; and provide power toprocessor engagement memory, wherein at least the processor is poweredOFF while the processor engagement memory is powered ON and wherein thememory is electrically coupled to the processor.
 8. The device of claim7, wherein the processor engagement memory is SDRAM.
 9. The device ofclaim 7, wherein the application portion is operative to operateaccording to one of at least three application power modes, wherein thecarrier portion is operative to operate according to one of at leastthree carrier power modes, and wherein the power management circuitry isoperative to coordinate which application power mode and which carrierpower mode the application and carrier portions operate in at any giventime during operation of the device.
 10. The device of claim 7, whereinthe power management circuitry is operative to operate the applicationportion in a HIBERNATION mode.
 11. The device of claim 7, wherein thepower management circuitry is operative to operate the applicationportion in an OFF mode, a DEEP SLEEP mode, a SLEEP mode, a HIBERNATIONmode, and an ON mode.
 12. The device of claim 7, wherein the powermanagement circuitry is operative to operate the carrier portion in anOFF mode, a SLEEP mode, and an ON mode.
 13. The device of claim 7,wherein the power management is operative to: operate the carrierportion in a SLEEP mode; temporarily activate predetermined circuitry inthe carrier portion to determine whether an incoming signal is beingreceived; and in response to determining that an incoming signal isbeing received, switching the carrier portion from the SLEEP mode to anON mode.
 14. The device of claim 13, wherein temporarily activatingpredetermined circuitry is performed when the carrier portion is in theSLEEP mode.
 15. The device of claim 7, wherein the power managementcircuitry comprises: application portion power management circuitry; andcarrier portion power management circuitry.
 16. The device of claim 7,wherein the device is mobile telephone.